An efficient VLSI architecture for 4 × 4 16-QAM sorted QR-factorisation based V-BLAST decoder

Document Type

Article

Publication Date

5-2011

Department

Department of Electrical and Computer Engineering

Abstract

This paper presents a practically realisable VLSI architecture for a 4 × 4 16-QAM MIMO wireless communication system using the Vertical Bell Labs Layered Space-Time (V-BLAST) detection scheme. The proposed implementation employs the QR-factorisation technique. The design and optimisation of the pre-decoder block are carried out using the COordinate Rotation DIgital Computer (CORDIC) processors. In order to avoid the numerical problems associated with Back Substitution (BS) based Symbol Interference Cancellation (SIC), a modified BS-SIC architecture that eliminates the need for division and multiplication is proposed. Not only does this substantially reduce the hardware cost, but also enjoys improved numerical stability. As the decoder hardware design can also be simplified by rendering it oblivious to the power normalisation in the transmitter side of the MIMO wireless system, we have designed a matching compensation unit at the receiver. The resulting VLSI architecture was implemented on an Altera Stratix Field Programmable Gate Array (FPGA) platform and on a 0.18 μm Application Specific Integrated Circuits (ASIC) platform. Detection throughput ratings of 149 Mbps and 212 Mbps were achieved. However, the lower hardware complexity of the BS-SIC based decoder architecture comes at the cost of a degradation in the Bit Error Rate (BER) performance with respect to the original higher complexity V-BLAST. Therefore, we also propose a novel parallel decoding scheme that is aimed at improving the system BER. This novel scheme allows for a compromise between the hardware overhead and the BER performance. As the hardware complexity is increased, the performance approaches the original V-BLAST limit.

Publication Title

AEU - International Journal of Electronics and Communications

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