Design of a Costas loop down converter
Document Type
Conference Proceeding
Publication Date
12-1-2009
Abstract
This paper presents the the design of a digital down converter (DDC) using a digital Costas loop in a field programmable gate array (FPGA). To reduce the power dissipation we use the CIC filter to perform an efficient decimation, and then follow it with a finite impulse response (FIR) compensation filter that runs at a reduced sampling rate. The final results and performance measures are quantified and discussed. The BER performance of the Costas loop on both floating and fixed point implementations are identical. © 2009 IEEE.
Publication Title
Midwest Symposium on Circuits and Systems
Recommended Citation
Roddewig, M.,
Zekavat, S.,
&
Nooshabadi, S.
(2009).
Design of a Costas loop down converter.
Midwest Symposium on Circuits and Systems, 244-247.
http://doi.org/10.1109/MWSCAS.2009.5236106
Retrieved from: https://digitalcommons.mtu.edu/michigantech-p/10816