Design and implementation of a costas loop down converter in FPGA
Document Type
Conference Proceeding
Publication Date
12-1-2009
Abstract
This paper presents the the design of a digital down converter (DDC) using a digital Costas loop in a field programmable gate array (FPGA). The designed DDC is one of the modules in the receiver of the base station in a wireless local positioning systems (WLPS). WLPS is capable of localization in the GPS-denied environments such as indoor and underground. The final results and performance measures are quantified and discussed. At the bit error rate (BER) of 10-4 our fixed point implementation of the demodulator using the Costas loop performs only 0.125 dB worst than the theoretical limit.
Publication Title
2009 5th IEEE GCC Conference and Exhibition, GCC 2009
Recommended Citation
Roddewig, M.,
Zekavat, S.,
&
Nooshabadi, S.
(2009).
Design and implementation of a costas loop down converter in FPGA.
2009 5th IEEE GCC Conference and Exhibition, GCC 2009.
http://doi.org/10.1109/IEEEGCC.2009.5734325
Retrieved from: https://digitalcommons.mtu.edu/michigantech-p/10616