Date of Award
2018
Document Type
Open Access Master's Report
Degree Name
Master of Science in Computer Engineering (MS)
Administrative Home Department
Department of Electrical and Computer Engineering
Advisor 1
Saeid Nooshabadi
Committee Member 1
Roger Kieckhafer
Committee Member 2
Soner Onder
Abstract
Flash memory has become increasingly popular as the underlying storage technology for high-performance nonvolatile storage devices. However, while flash offers several benefits over alternative storage media, a number of limitations still exist within the current technology. One such limitation is that programming (altering a bit from its default value) and erasing (returning a bit to its default value) are asymmetric operations in flash memory devices: a flash memory can be programmed arbitrarily, but can only be erased in relatively large batches of storage bits called blocks, with block sizes ranging from 512K up to several megabytes. This creates a situation where relatively small write operations to the drive can potentially require reading out, erasing, and rewriting many times more data than the initial operation would normally require if that write would result in a bit erase operation. Prior work suggests that the performance impact of these costly block erase cycles can be mitigated by using a rewriting code, increasing the number of writes that can be performed on the same location in memory before an erase operation is required. This paper provides an implementation of this rewriting code, both as a software program written in C and as a SystemVerilog FPGA circuit specification, and discusses many of the additional design considerations that would be necessary to integrate such a rewriting code with current file storage techniques.
Recommended Citation
Druschke, Vincent T., "Implementing Write Compression in Flash Memory Using Zeckendorf Two-Round Rewriting Codes", Open Access Master's Report, Michigan Technological University, 2018.
Source file for software implementation
FZcompress.h (5 kB)
Header file for software implementation
FZEncodeWordSeq.sv (1 kB)
Encode module descriptor for hardware implementation
FZDecodeWordSeq.sv (1 kB)
Decode module descriptor for hardware implementation
FZPadBitsSeq.sv (1 kB)
Padding module descriptor for hardware implementation
FZOverwriteSeq.sv (2 kB)
Overwrite module descriptor for hardware implementation
FZExtractSeq.sv (2 kB)
Extract module descriptor for hardware implementation
FZCompressSeq.sv (5 kB)
Top-level module descriptor for hardware implementation, incorporates all hardware sub-modules into single circuit