Date of Award
2022
Document Type
Open Access Master's Thesis
Degree Name
Master of Science in Computer Science (MS)
Administrative Home Department
Department of Computer Science
Advisor 1
Soner Onder
Committee Member 1
Zhenlin Wang
Committee Member 2
Jianhui Yue
Committee Member 3
David Whalley
Abstract
We introduce a novel fetch architecture called Poor Man’s Trace Cache (PMTC). PMTC constructs taken-path instruction traces via instruction replication in static code and inserts them after unconditional direct and select conditional direct control transfer instructions. These traces extend to the end of the cache line. Since available space for trace insertion may vary by the position of the control transfer instruction within the line, we refer to these fetch slots as variable delay slots. This approach ensures traces are fetched along with the control transfer instruction that initiated the trace. Branch, jump and return instruction semantics as well as the fetch unit are modified to utilize traces in delay slots. PMTC yields the following benefits: 1. Average fetch bandwidth increases as the front end can fetch across taken control transfer instructions in a single cycle. 2. The dynamic number of instruction cache lines fetched by the processor is reduced as multiple non contiguous basic blocks along a given path are encountered in one fetch cycle. 3. Replication of a branch instruction along multiple paths provides path separability for branches, which positively impacts branch prediction accuracy. PMTC mechanism requires minimal modifications to the processor’s fetch unit and the trace insertion algorithm can easily be implemented within the assembler without compiler support.
Recommended Citation
Moore, Tino C., "POOR MAN’S TRACE CACHE: A VARIABLE DELAY SLOT ARCHITECTURE", Open Access Master's Thesis, Michigan Technological University, 2022.