Date of Award

2016

Document Type

Open Access Master's Thesis

Degree Name

Master of Science in Mechanical Engineering (MS)

Administrative Home Department

Department of Mechanical Engineering-Engineering Mechanics

Advisor 1

Mahdi Shahbakhti

Committee Member 1

Jeremy J. Worm

Committee Member 2

Mohsen Azizi

Abstract

Premixed compression ignition (PCI) technologies offer high efficiency and low emissions but are usually confined by limited operation range as well as high pressure rise and heat release rate. In this work, a more recently developed PCI mode is explored where in-cylinder blending of two fuels with different auto-ignition characteristics (diesel and gasoline) is utilized to create reactivity stratification such that heat release rate and combustion timing can be controlled. This mode has been defined as Reactivity Controlled Compression Ignition (RCCI).

As part of this thesis, the main aim is to study various parameters that can be used to control combustion phasing. Also, steady state mapping of the engine is done so as to explore the operating range for the current engine setup. Best efficiencies as well as highest loads are obtained for higher Premixed Ratio (PR) values and advanced Start of Injection (SOI) timings, where as lower PR fuel blends are needed to achieve low load limit. The analysis is also extended to transient RCCI operation for observing various dynamics involved and their effects on combustion phasing. As part of realizing full-load range operation, switching to conventional Spark-Ignition (SI) combustion mode is also carried out. Various dynamics involved in the switching process are captured.

A cycle-by-cycle closed loop combustion controller is designed and implemented on the engine to achieve optimum combustion phasing during transient engine operation. To provide feedback of combustion parameters like engine load and combustion phasing to the closed loop controller, a real-time combustion feedback system is designed and implemented utilizing Field Programmable Gate Array (FPGA).

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