Date of Award
2022
Document Type
Open Access Master's Thesis
Degree Name
Master of Science in Computer Science (MS)
Administrative Home Department
Department of Computer Science
Advisor 1
Soner Onder
Committee Member 1
Zhenlin Wang
Committee Member 2
Jianhui Yue
Committee Member 3
David Whalley
Abstract
Modern superscalar processors are able to potentially issue and execute multiple instructions per cycle. Several techniques over the years have focused on increasing the Instruction Level Parallelism (ILP) that a processor can exploit. However, there are many limitations of ILP that hinder performance, chief of them being the chain of dependencies between instructions that stops instructions from being executed in parallel.
We propose a new micro-architecture design which extends the superscalar pipeline with a data-flow pipeline where the dataflow part identifies immediately dependent instructions and executes them early. The dataflow pipeline is able to identify redundant instructions, track changes in the operands of the redundant instructions and execute new instructions early in case of operand change. Our design helps alleviate some of the main limitations of ILP.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Kasad, Kurush, "Eager Scheduling of Dependent Instructions", Open Access Master's Thesis, Michigan Technological University, 2022.