mPart: miss-ratio curve guided partitioning in key-value stores
Document Type
Conference Proceeding
Publication Date
2018
Department
Department of Computer Science; Center for Data Sciences; Center for Scalable Architectures and Systems
Abstract
Web applications employ key-value stores to cache the data that is most commonly accessed. The cache improves an web application's performance by serving its requests from memory, avoiding fetching them from the backend database. Since the memory space is limited, maximizing the memory utilization is a key to delivering the best performance possible. This has lead to the use of multi-tenant systems, allowing applications to share cache space. In addition, application data access patterns change over time, so the system should be adaptive in its memory allocation.
In this work, we address both multi-tenancy (where a single cache is used for multiple applications) and dynamic workloads (changing access patterns) using a model that relates the cache size to the application miss ratio, known as a miss ratio curve. Intuitively, the larger the cache, the less likely the system will need to fetch the data from the database. Our efficient, online construction of the miss ratio curve allows us to determine a near optimal memory allocation given the available system memory, while adapting to changing data access patterns. We show that our model outperforms an existing state-of-the-art sharing model, Memshare, in terms of overall cache hit ratio and does so at a lower time cost. We show that for a typical system, overall hit ratio is consistently 1 percentage point greater and 99.9th percentile latency is reduced by as much as 2.9% under standard web application workloads containing millions of requests.
Publication Title
Proceedings of the 2018 ACM SIGPLAN International Symposium on Memory Management
Recommended Citation
Byrne, D.,
Onder, N.,
&
Wang, Z.
(2018).
mPart: miss-ratio curve guided partitioning in key-value stores.
Proceedings of the 2018 ACM SIGPLAN International Symposium on Memory Management, 84-95.
http://doi.org/10.1145/3299706.3210571
Retrieved from: https://digitalcommons.mtu.edu/michigantech-p/739
Publisher's Statement
© 2018 Association for Computing Machinery. Publisher's version of record: https://doi.org/10.1145/3299706.3210571