Novel low-latency, high-resolution and low-cost time synchronisation

Authors

Ali Aghdaei, Michigan Technological UniversityFollow
Seyed A. Zekavat, Michigan Technological UniversityFollow

Document Type

Article

Publication Date

12-7-2017

Department

Center for Cyber-Physical Systems; Department of Electrical and Computer Engineering

Abstract

This study presents an oversampling-based low-latency, high-resolution and low-cost timing synchronisation technique for digital receivers. Traditional timing synchronisation employs matched filter to estimate the signal coarse time of arrival. Here, latency increases through oversampling and resolution improves via higher bandwidth. The proposed method uses single bit quantisation to employ XNOR blocks instead of multiplier and accumulator blocks in the traditional method. This substantially decreases complexity incorporating less field-programmable gate array (FPGA) surface area.

Publisher's Statement

© The Institution of Engineering and Technology 2017. Publisher's version of record: https://doi.org/10.1049/iet-wss.2017.0025

Publication Title

IET Wireless Sensor Systems

Recommended Citation

Aghdaei, A., & Zekavat, S. A. (2017). Novel low-latency, high-resolution and low-cost time synchronisation. IET Wireless Sensor Systems, 7(6), 178-181. http://doi.org/10.1049/iet-wss.2017.0025
Retrieved from: https://digitalcommons.mtu.edu/michigantech-p/656