Modeling and analyzing timing faults in transaction level SystemC programs

Document Type

Conference Proceeding

Publication Date

12-1-2013

Department

Department of Computer Science

Abstract

In order to increase design productivity of SoC (System on Chip) systems, there is a need to move from implementation-driven design at Register Transfer Language (RTL) to higher levels of abstraction. This move introduces a shift in the development of electronic systems, which has been put into practice as Electronic System Level (ESL) design. The importance of ESL has become reality with Transaction Level Modeling (TLM) standard TLM-2.0 [1]. The C++-based system modeling language SystemC perfectly supports TLM and hence is well-accepted for ESL design in industry.

Publication Title

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

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