CATALYST: Planning layer directives for effective design closure
Document Type
Conference Proceeding
Publication Date
5-6-2013
Department
Department of Electrical and Computer Engineering
Abstract
For the last several technology generations, VLSI designs in new technology nodes have had to confront the challenges associated with reduced scaling in wire delays. The solution from industrial back-end-of-line process has been to add more and more thick metal layers to the wiring stacks. However, existing physical synthesis tools are usually not effective in handling these new thick layers for design closure. To fully leverage these degrees of freedom, it is essential for the design flow to provide better communication among the timer, the router, and different optimization engines. This work proposes a new algorithm, CATALYST, to perform congestion- and timing-aware layer directive assignment. Our flow balances routing resources among metal stacks so that designs benefit from the availability of thick metal layers by achieving improved timing and buffer usage reduction while maintaining routability. Experiments demonstrate the effectiveness of the proposed algorithm.
Publication Title
Proceedings -Design, Automation and Test in Europe, DATE
Recommended Citation
Wei, Y.,
Li, Z.,
Sze, C.,
Hu, S.,
Alpert, C.,
&
Sapatnekar, S.
(2013).
CATALYST: Planning layer directives for effective design closure.
Proceedings -Design, Automation and Test in Europe, DATE, 1873-1878.
http://doi.org/10.7873/date.2013.373
Retrieved from: https://digitalcommons.mtu.edu/michigantech-p/3284
Publisher's Statement
© 2013 EDAA. Publisher’s version of record: https://doi.org/10.7873/date.2013.373