A Spectral Approach to Scalable Vectorless Thermal Integrity Verification

Document Type

Conference Proceeding

Publication Date

3-1-2020

Department

Department of Electrical and Computer Engineering

Abstract

Existing chip thermal analysis and verification methods require detailed distribution of power densities or modeling of underlying input workloads (vectors), which may not always be feasible at early-design stage. This paper introduces the first vectorless thermal integrity verification framework that allows computing worst-case temperature (gradient) distributions across the entire chip under a set of local and global workload (power density) constraints. To address the computational challenges introduced by the large 3D mesh-structured thermal grids, we propose a novel spectral approach for highly-scalable vectorless thermal verification of large chip designs. Our approach is based on emerging spectral graph theory and graph signal processing techniques, which consists of a thermal grid topology sparsification phase, an edge weight scaling phase, as well as a solution refinement procedure. The effectiveness and efficiency of our approach have been demonstrated through extensive experiments.

Publisher's Statement

© 2020 EDAA. Publisher’s version of record: https://doi.org/10.23919/DATE48585.2020.9116438

Publication Title

Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020

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