Efficient NVM Crash Consistency by Mitigating Resource Contention

Document Type

Conference Proceeding

Publication Date

11-22-2021

Department

Department of Computer Science

Abstract

Logging is widely adopted to ensure crash consistency for Non-Volatile Memory (NVM) systems. However, the logging imposes significant performance overhead caused by the extra log operations and ordering constraints between the logging and in-place updates, degrading the system performance. There are some research efforts to reduce the logging overhead. Recently, LAD proposed that exploiting the non-volatility of Asynchronous DRAM Refresh (ADR) buffer can remove log operations for a transaction whose total amount of updated cachelines is smaller than the buffer capacity, ensuring crash consistency. However, on multi-core systems, concurrent transactions contend the scarce ADR buffer and frequently lead to the buffer overflow. Upon the buffer overflow, LAD resorts to logging operations for in-flight transactions, degrading the system performance. Our experiments show that LAD produces a significant number of log operations when multiple transactions run concurrently. To decrease log operations caused by LAD, this paper presents a new transaction execution scheme, called two-stage transaction execution(TSTE), which allows the write requests of a transaction to be in both the ADR buffer and the staging SRAM buffer. Our new scheme performs log operations for a transaction's write requests in the SRAM buffer and executes in-place update operations for this transaction's write requests in the ADR buffer. The introduced SRAM buffer can make the ADR buffer serve more update requests, reducing log operations.The evaluation results demonstrate that our proposed schemes can efficiently reduce log operations up to 39.29% and improve the transaction throughput up to 28.22%

Publication Title

2021 IEEE International Conference on Networking, Architecture and Storage, NAS 2021 - Proceedings

ISBN

9781728177441

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