JLS: A pedagogically targeted logic design and simulation tool
Document Type
Conference Proceeding
Publication Date
12-15-2008
Abstract
JLS is a GUI-based digital logic simulation tool specifically designed for use in a wide range of digital logic and computer organization courses. It is comparable in features and functionality to commercial products, but includes many student and instructor-friendly aspects not found in those products such as state-machine and truth table editors, extensive error checking, and multiple simulation result views. Students quickly become proficient in its use, enabling them to concentrate on circuit design and debugging issues. The circuit drawing interface is convenient enough to allow instructors to use it for classroom presentations, and circuits can be modified and tested so quickly that it promotes exploring alternatives not prepared for in advance.
Publication Title
Proceedings of the Conference on Integrating Technology into Computer Science Education, ITiCSE
Recommended Citation
Poplawski, D.,
&
Kurmas, Z.
(2008).
JLS: A pedagogically targeted logic design and simulation tool.
Proceedings of the Conference on Integrating Technology into Computer Science Education, ITiCSE, 314.
http://doi.org/10.1145/1384271.1384357
Retrieved from: https://digitalcommons.mtu.edu/michigantech-p/12489