Thermal stresses in layered electronic assemblies

Document Type

Article

Publication Date

1-1-1997

Abstract

Thermal stresses in layered electronic assemblies are one of the causes of the mechanical failure of electronic packages. A simple but accurate method of estimating these thermal stresses is needed for the design of these packages. A simple approach based on beam theory exists, but it suffers from nonequilibrium of the peeling stress distribution. An improved method that overcomes this drawback is proposed here. For layered electronics with thin adhesives, simple analytical expressions are obtained/or interfacial shear stress and peeling stress, as well as for other stress components. The finite element method is used to verify these solutions. It shows excellent agreement between the finite element results and these simple solutions, especially when the moduli of adhesive layers are significantly lower than the moduli of the other layers. This method provides an accurate estimate of thermal stresses for use in package design involving thin and compliant interface or adhesive layers. © 1997 ASME.

Publication Title

Journal of Electronic Packaging, Transactions of the ASME

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