Scalable multilevel vectorless power grid voltage integrity verification

Document Type

Article

Publication Date

1-1-2013

Abstract

With the current aggressive integrated circuit technology scaling, vectorless power grid voltage integrity verification becomes key to designing reliable power delivery networks. To address the challenges of existing vectorless power grid verification methods that suffer from excessively long optimization time and poor scalability to large power grid designs, in this paper, we present a scalable multilevel vectorless power grid verification method which can efficiently tackle very large scale power grid verifications. By taking advantage of a series of coarsest to coarser grid verifications, the finest power grid verification can be accomplished in a more efficient way. To gain good efficiency, global and local 'critical regions' for power grid verification are introduced, while power grid structure and electrical properties are exploited to facilitate identifying the worst case voltage drops across the entire chip. The proposed multilevel power grid verification algorithm allows more flexible tradeoffs between verification cost and solution quality, while providing the desired conservative upper/lower bounds for worst case voltage drops. Extensive experimental results show that our approach can efficiently handle very large power grid designs without sacrificing the final power grid verification accuracy. For example, finding the worst voltage drop for a flip-chip power grid design with one million nodes takes less than two hours. © 1993-2012 IEEE.

Publication Title

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Link to Full Text

Share

COinS