Efficient checking of power delivery integrity for power gating
Document Type
Conference Proceeding
Publication Date
6-22-2011
Abstract
Multi-core architecture has emerged as the primary architectural choice to achieve power-efficient computing in microprocessors and SoCs. Power gating is indispensable for system power and thermal management and well suited for multi-core architectures. However, checking the power integrity (such as electromigration and voltage drop) of large gated power delivery networks (PDNs) presents a significant challenge due to the sheer die-package network complexity and the existence of an extremely large number of possible gating and operation configurations. We propose a simulation-based checking methodology that encompasses a comprehensive set of essential checking tasks. We tackle the challenges brought by the large checking space by developing strategies that efficiently identify top-ranked worst-case operating conditions, which are sequentially analyzed through a well-controlled number of full simulations for fidelity. We demonstrate the superior performance of the proposed approach on large power gating checking problems that are completely intractable to brute-force methods. © 2011 IEEE.
Publication Title
Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
Recommended Citation
Zeng, Z.,
Feng, Z.,
&
Li, P.
(2011).
Efficient checking of power delivery integrity for power gating.
Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, 663-670.
http://doi.org/10.1109/ISQED.2011.5770800
Retrieved from: https://digitalcommons.mtu.edu/michigantech-p/10689
