A polynomial time approximation scheme for timing constrained minimum cost layer assignment

Document Type

Conference Proceeding

Publication Date

12-26-2008

Abstract

As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming Increasingly resistive which makes it more difficult to propagate signals across the chip. However, more advanced technologies (65nm and 45nm) provide relief as the number of metal layers continues to increase. The wires on the upper metal layers are much less resistive and can be used to drive further and faster than on thin metals. This provides an entirely new dimension to the traditional wire sizing problem, namely, layer assignment for efficient timing closure. Assigning all wires to thick metals improves timing, however, mutability of the design may be hurt. The challenge is to assign minimal amount of wires to thick metals to meet timing constraints. In this paper, the minimum cost layer assignment problem is proven to be NP-Complete. As a theoretical solution for NP-complete problems, a polynomial time approximation scheme is proposed. The new algorithm can approximate the optimal layer assignment solution by a factor of 1 + ε In O(m log log m · n 3/ε2) time for O < e ε 1, where n is the number of nodes in the tree and m is the number of routing layers. This work presents the first theoretical advance for the timing-driven minimum cost layer assignment problem. In addition to its theoretical guarantee, the new algorithm is highly practical. Our experiments on 500 testcases demonstrate that the new algorithm can run 2 × faster than the optimal dynamic programming algorithm with only 2% additional wire.

Publication Title

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

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