Implementation of fault-tolerant sequential circuits using programmable logic arrays
Document Type
Conference Proceeding
Publication Date
1-1-1991
Abstract
© 1991 IEEE. An efficient implementation procedure has been developed for the realization of sequential circuits using PLAs. The synthesis procedure is simple and based on a heuristic approach. Synchronous sequential circuits which have been widely used in digital computers over the years can be easily implemented in a single chip layout. One of the major advantages of this method is the reduction in chip area in terms of the fusible links blown to realize the state machine using PLAs.
Publication Title
Proceedings - 1st Great Lakes Symposium on VLSI, GLSV 1991
Recommended Citation
Misra, N.,
&
Goel, A.
(1991).
Implementation of fault-tolerant sequential circuits using programmable logic arrays.
Proceedings - 1st Great Lakes Symposium on VLSI, GLSV 1991, 128-131.
http://doi.org/10.1109/GLSV.1991.143954
Retrieved from: https://digitalcommons.mtu.edu/michigantech-p/10512