Impact of NoFPGA IP router architecture on link bandwidth

Document Type

Conference Proceeding

Publication Date

9-15-2008

Abstract

In today's world of advanced technology numerous applications are computationally intensive. This created an opportunity for the development of new System-on-Chip (SoC) design techniques to allow easy IP cores (Intellectual Property cores) re-use and integration under time-to-market pressure. A wide range of these newly emerging design platforms is now drifting towards highly integrated System-on-Chip designs with many on-chip processing resources like processors, DSPs, and memories. Using this technique, designers can build System-on-Chip (SoC) by integrating dozens of IP cores. As the number of IP cores integrated on a chip increases, the on-chip communication and physical interconnections become a bottleneck. New System-on-Chip (SoC) design techniques are necessary to address the communication requirements for future SoC. New communication architecture, the NoFPGA (Network-on-FPGA), for future SoFPGA (System-on-FPGA) has been presented. The paper details the architecture of a NoFPGA router. The interconnecting issues in SoFGPA design methodology built in a single FPGA device are addressed. Mainly, the performance analysis of the IPRouter of both Torus and Mesh topologies is addressed. © 2008 IEEE.

Publication Title

2008 IEEE International Conference on Electro/Information Technology, IEEE EIT 2008 Conference

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