Date of Award

2024

Document Type

Open Access Dissertation

Degree Name

Doctor of Philosophy in Computer Science (PhD)

Administrative Home Department

Department of Computer Science

Advisor 1

Zhenlin Wang

Committee Member 1

Soner Onder

Committee Member 2

Jianhui Yue

Committee Member 3

Xiaoyong Yuan

Abstract

To minimize the latency of accessing back-end servers, modern web services often use in-memory key-value (k-v) stores at the front end to cache frequently accessed objects. Due to the limited memory capacity, these stores must be configured with a fixed amount of memory. Consequently, cache replacement is required when the footprint of the accessed objects exceeds the cache size.

This thesis presents a comprehensive exploration of advanced dynamic memory management techniques for k-v stores. The first study conducts a detailed analysis of K-LRU, a random sampling-based replacement policy, proposing a dynamic K configuration scheme to exploit the potential miss ratio gap among various Ks. Experimental results demonstrate a throughput improvement of up to 32.5% over the default static K setting.

Building on this, the second study extends the exploration of K-LRU to a multi-tenant k-v store environment, introducing a locality- and latency-aware memory partitioning scheme. This approach significantly enhances performance, achieving up to a 50.2% reduction in average access latency and a 262.8% increase in throughput compared to standard Redis. When compared to a state-of-the-art memory allocation design, the proposed scheme shows improvements of up to 24.8% in average access latency and 61.8% in throughput.

Finally, inspired by emerging Compute Express Link (CXL) memory-sharing techniques, the third study pushes k-v store memory management into a multi-tier memory environment. This involves designing a software-defined tiered memory management architecture on top of a CXL memory-sharing switch. By dynamically identifying hot application data, efficiently migrating items among memory tiers based on popularity, and implementing multi-tenant memory partitioning, the proposed sdTMM system effectively integrates fast local DRAM with slower but larger CXL-shared memory. Evaluations across various workloads show that, even with 80% of the fast memory replaced by CXL-shared slow memory, sdTMM maintains an average performance impact of 13%, with the best-case impact as low as 2.2% compared to an all-fast memory over-provisioned system.

This research collectively advances the techniques of dynamic memory management, demonstrating promising performance improvements in k-v stores.

Creative Commons License

Creative Commons Attribution 4.0 License
This work is licensed under a Creative Commons Attribution 4.0 License.

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