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Abstract

Micro-architecture designs and methods are provided. A computer processing architecture may include an instruction cache for storing producer instructions, a half-instruction cache for storing half instructions, and eager shelves for storing a result of a first producer instruction. The computer processing architecture may fetch the first producer instruction and a first half instruction; send the first half instruction to the eager shelves; based on execution of the first producer instruction, send a second half instruction to the eager shelves; assemble the first producer instruction in the eager shelves based on the first half instruction and the second half instruction; and dispatch the first producer instruction for execution.

Patent Number

11,188,337

Assignee

The Florida State University Research Foundation, Inc.

Assignee

Michigan Technological University

Date Filed

9-30-2019

Certificate of Correction

No

Issue Date

11-30-2021

Micro-architecture designs and methods for eager execution and fetching of instructions

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