Title

Micro-architecture designs and methods for eager execution and fetching of instructions

Inventors

David Whalley, Florida State University
Soner Onder, Michigan Technological UniversityFollow

Files

Abstract

Micro-architecture designs and methods are provided. A computer processing architecture may include an instruction cache for storing producer instructions, a half-instruction cache for storing half instructions, and eager shelves for storing a result of a first producer instruction. The computer processing architecture may fetch the first producer instruction and a first half instruction; send the first half instruction to the eager shelves; based on execution of the first producer instruction, send a second half instruction to the eager shelves; assemble the first producer instruction in the eager shelves based on the first half instruction and the second half instruction; and dispatch the first producer instruction for execution.

Patent Number

US 11,188,337 B2

Assignee

The Florida State University Research Foundation, Inc.

Assignee

Michigan Technological University

Date Filed

9-30-2019

Certificate of Correction

No

Issue Date

11-30-2021

Comments

For the most up-to-date information about this patent, including the availability of Certificates of Correction, be sure to check the United States Patent and Trademark Office's free, publicly accessible database: Patent Public Search https://ppubs.uspto.gov/pubwebapp/static/pages/landing.html

Recommended Citation

Whalley, David and Onder, Soner, "Micro-architecture designs and methods for eager execution and fetching of instructions" (2021). Michigan Tech Patents. 154.
https://digitalcommons.mtu.edu/patents/154