An algorithm for the speed optimization of multilevel carry skip adders
We develop a time-position algorithm that results in higher bits per group of the carry skip adder than reported earlier. In other words, this results in a bigger adder that computes in less time than with the other existing algorithms. An approach based on absolute gate delays is used. Performance of the carry skip adders using the developed algorithm has been compared with those of the competing carry ripple and the carry look-ahead adders. The results have been further validated by making models of the adder and simulating them in VHDL.
International Journal of Modelling and Simulation
An algorithm for the speed optimization of multilevel carry skip adders.
International Journal of Modelling and Simulation,
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