Improving energy efficiency by memoizing data access information
Department of Computer Science
Level-one data cache (L1 DC) and data translation lookaside buffer (DTLB) accesses impact energy usage as they frequently occur and each L1 DC and DTLB access uses significantly more energy than a register file access. Often, multiple memory operations will reference the same cache line using the same register, such as when iterating through an array. We propose to memoize L1 DC access information, such as the L1 DC data array way and the DTLB way, by associating this information with the register used to access it. When a load or store calculates the memory address, we detect whether the calculated address shares the cache line memoized with the base register. If so, we avoid the L1 DC tag array access and the DTLB access to determine the L1 DC way and instead use the memoized information. In addition, only a single data array way in a set-associative L1 DC needs to be accessed during a load instruction when the L1 DC way has been memoized. Our nonspeculative memoization approach can be applied before a speculative approach, allowing a significant reduction in data access energy usage for existing executables with no ISA modifications.
2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
Improving energy efficiency by memoizing data access information.
2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).
Retrieved from: https://digitalcommons.mtu.edu/michigantech-p/901
Copyright © 2019, IEEE. Publisher’s version of record: https://doi.org/10.1109/ISLPED.2019.8824951