Power-adaptive microarchitecture and compiler design for mobile computing

Document Type

Technical Report

Publication Date



Department of Computer Science


This project considered various sources of power consumption in general purpose high-performance and embedded processors and developed techniques for lowering the power consumption without significant sacrifice in performance. We have designed low power data caches and low power external data buses that can he used for both superscalar and embedded processors. For superscalar processors we have designed low complexity memory disambiguation mechanism, power efficient instruction issue mechanism, and load/store reuse techniques. For embedded processors we have developed techniques that allow us to achieve performance while operating on compacted code and data. The various techniques that were developed have been implemented as part of gcc compiler and the FAST simulation system. Experimentation was carried to demonstrate the utility of the techniques.

Publisher's Statement

©2002. Publisher’s version of record: https://apps.dtic.mil/docs/citations/ADA416016