Facilitating the design of fault tolerance in transaction level SystemC programs
Due to their increasing complexity, today's SoC (system on chip) systems are subject to a variety of faults (e.g., single-event upset, component crash, etc.), thereby making fault tolerance a highly important property of such systems. However, designing fault tolerance is a complex task in part due to the large scale of integration of SoC systems and different levels of abstraction provided by modern system design languages such as SystemC. Most existing methods enable fault injection and impact analysis as a means for increasing design dependability. Nonetheless, such methods provide little support for designing fault tolerance. To facilitate the design of fault tolerance in SoC systems, this paper proposes an approach for designing fault-tolerant inter-component communication protocols in SystemC transaction level modeling (TLM) programs. The proposed method includes four main steps, namely model extraction, fault modeling, addition of fault tolerance and refinement of fault tolerance to SystemC code. We demonstrate the proposed approach using a simple SystemC transaction level program that is subject to communication faults. Moreover, we illustrate how fault tolerance can be added to SystemC programs that use the base protocol of the TLM interoperability layer. We also illustrate how fault tolerance functionalities can be partitioned to software and hardware components. Finally, we put forward a roadmap for future research at the intersection of fault tolerance and hardware-software co-design. © 2012 Elsevier B.V. All rights reserved.
Theoretical Computer Science
Facilitating the design of fault tolerance in transaction level SystemC programs.
Theoretical Computer Science,
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