High performance CMOS level up shifter with full–scale 1.2 V output voltage

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© 2018 Elsevier Ltd This paper introduces a very low static current CMOS level up shifter for low voltage single supply and high performance. The proposed low to high voltage level shifter is implemented using low threshold voltage transistors in 65 nm CMOS technology and based on differential topology. The shifter circuit was designed to be functional for an input voltage from 0.45 up to 1.2 V. Driving a 450 fF of capacitive load, the shifter's energy–delay product (EPD) is a 54% lower than a similar single supply level up shifter. Post–layout simulations, for every technological corner, temperature range from 25 up to 125 °C, operating input voltages and output capacitive loads (maximum of 740 fF), demonstrate the topology is fully functional without any impact on the static power consumption and the operating frequency of 500 MHz. Monte Carlo analysis shows the robustness of the proposed shifter within a 3σ device mismatch.

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Microelectronics Journal