Electrode parasitic capacitances in self-aligned and deep-recessed GaAs MESFETs
Document Type
Article
Publication Date
10-1988
Department
Department of Electrical and Computer Engineering
Abstract
We have developed an efficient algorithm for the determination of the electrode parasitic capacitances in self-aligned and deep-recessed single-gate GaAs MESFETs. The model has been used to study the dependence of these capacitances on the MESFET dimensions. Self capacitances of the source, gate and drain electrodes and the coupling capacitances between pairs of them are calculated for several values of the source, gate and drain lengths, source-gate and gate-drain separations, device widths, substrate thicknesses and heights of the electrodes above the bottom ground plane. Results include the fringing fields as well as the shielding due to the neighboring electrodes. The method of moments in conjunction with a Green's function appropriate to the geometry of the MESFET is employed. Values of the electrode parasitic capacitances for a few typical GaAs MESFETs have been compared with those of the internal capacitances in them.
Publication Title
Solid State Electronics
Recommended Citation
Goel, A.
(1988).
Electrode parasitic capacitances in self-aligned and deep-recessed GaAs MESFETs.
Solid State Electronics,
31(10), 1471-1476.
http://doi.org/10.1016/0038-1101(88)90017-2
Retrieved from: https://digitalcommons.mtu.edu/michigantech-p/5496