Facilitating the design of fault tolerance in transaction level SystemC programs

Document Type

Conference Proceeding

Publication Date

1-17-2012

Department

Department of Computer Science

Abstract

Due to their increasing complexity, today's SoC (System on Chip) systems are subject to a variety of faults (e.g., soft errors, component crash, etc.), thereby making fault tolerance a highly important property of such systems. However, designing fault tolerance is a complex task in part due to the large scale of integration of SoC systems and different levels of abstraction provided by modern system design languages such as SystemC. Most existing methods enable fault injection and impact analysis as a means for increasing design dependability. Nonetheless, such methods provide little support for designing fault tolerance. To facilitate the design of fault tolerance in SoC systems, this paper propose an approach where fault tolerance is designed at the level of inter-component communication protocols in SystemC Transaction Level (TL) models. The proposed method includes four main steps, namely model extraction, fault modeling, addition of fault tolerance and refinement of synthesized fault tolerance to SystemC code. We demonstrate the proposed approach using a simple SystemC transaction level program that is subject to communication faults. We also provide a roadmap for future research at the intersection of fault tolerance and hardware-software co-design.

Publication Title

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

ISBN

978-3-642-25959-3

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