A pedagogically targeted logic design and simulation tool
JLS is a GUI-based digital logic simulation tool specifically designed for use in a wide range of digital logic and computer organization courses. It is comparable in features and functionality to commercial products, but includes many student and instructor-friendly aspects not found in those products such as state-machine and truth table editors, extensive error checking, and multiple simulation-result views. Students quickly become proficient in its use, enabling them to concentrate on circuit design and debugging issues. The circuit drawing interface is convenient enough to allow instructors to use it for classroom presentations, and circuits can be modified and tested so quickly that it promotes exploring alternatives not prepared for in advance. Its non-interractive (batch) execution capability, with parameter settings, configuration files and textual output simplifies the grading of large numbers of student projects. Copyright 2007 ACM.
Proceedings of the 2007 Workshop on Computer Architecture Education, WCAE'07
A pedagogically targeted logic design and simulation tool.
Proceedings of the 2007 Workshop on Computer Architecture Education, WCAE'07, 1-7.
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