Capacitance extraction for the nano-scale on-chip interconnects
Single-level and multi-path interconnect structures embedded in dielectrics on a silicon substrate are designed for simulation and capacitance extractions for these nano-scale three dimensional structures are done using the SILVACO® TCAD tools. Simulation results are used to study the dependences of the ground and coupling capacitances on the permittivity of the dielectric material used and the thickness of the overlapping dielectric in addition to the geometry of the interconnect structure. © 2004 IEEE.
Proceedings ICSE 2004 - 2004 IEEE International Conference on Semiconductor Electronics
Capacitance extraction for the nano-scale on-chip interconnects.
Proceedings ICSE 2004 - 2004 IEEE International Conference on Semiconductor Electronics, 112-116.
Retrieved from: https://digitalcommons.mtu.edu/michigantech-p/10924