Title

A hybrid equivalent-bit spacing scheme for low energy and high performance for bus signalling

Document Type

Conference Proceeding

Publication Date

9-20-2010

Abstract

Interconnects on deep submicron (DSM) buses incur significantly larger power dissipation, delay performance degradation, and induced signal interference due to coupling capacitance between adjacent wires on the bus. This paper proposes a novel encoding scheme to, further, reduce the coupling energy dissipation, and delay. Further, the energy cost of the overhead encoding scheme in our proposed scheme is significantly reduced. We present an 8-bit to 10-bit equivalent solution that reduces the energy dissipation by 55%, delay by 24%, and energy delay product by 65%, without any additional area penalty on the bus. It also requires much less complex codec circuitry requiring 96% less area overhead, when compared with transition pattern coding (TPC) scheme. Our analysis is based on 65nm CMOS technology. © 2010 IEEE.

Publication Title

Midwest Symposium on Circuits and Systems

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