Enabling Massive Multi-Threading with Fast Hashing
Document Type
Article
Publication Date
1-1-2018
Abstract
© 2017 IEEE. The next generation of high-performance computers is expected to execute threads in orders of magnitude higher than today's systems. Improper management of such huge amount of threads can create resource contention, leading to overall degraded system performance. By leveraging more practical approaches to distribute threads on the available resources, execution models and manycore chips are expected to overcome limitations of current systems. Here, we present DELTA - a Data-Enabled muLti-Threaded Architecture, where a producer-consumer scheme is used to execute threads via complete distributed thread management mechanism. We consider a manycore tiled-chip architecture where Network-on-Chip (NoC) routers are extended to support our execution model. The proposed extension is analysed, while simulation results confirm that DELTA can manage a large number of simultaneous threads, relying on a simple hardware structure.
Publication Title
IEEE Computer Architecture Letters
Recommended Citation
Scionti, A.,
Mazumdar, S.,
&
Zuckerman, S.
(2018).
Enabling Massive Multi-Threading with Fast Hashing.
IEEE Computer Architecture Letters,
17(1), 1-4.
http://doi.org/10.1109/LCA.2017.2697863
Retrieved from: https://digitalcommons.mtu.edu/michigantech-p/10744