An energy-efficient 1MSps 7W 11.9fJ/conversion step 7pJ/sample 10-bit SAR ADC in 90nm

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Conference Proceeding

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Current trends constantly increase the need for ultra-low power solutions for the embedded and portable hardware. One circuit component required in wide range of devices is the analog-to-digital converter (ADC). In this paper we propose an extremely energy-efficient successive approximation register (SAR) ADC, in which we have overcome the limitations of conventional approaches through topological improvements. Further, advances include a novel bootstrapped track and hold (T/H) circuitry. Statistical simulations indicate an ADC with a figure of merit (FOM) of 11.9 fJ per conversion step, and an effective number of bits (ENOB) of 9.2, operating close to Nyquist frequency, sampling at 1 Msps. To put it into perspective, consuming only 7 pJ/sample, this ADC is able to work at its maximum speed for more than 40 years with the total energy of a single alkaline AA battery. © 2011 IEEE.

Publication Title

Proceedings - IEEE International Symposium on Circuits and Systems