Title

High performance dual supply level up/down shifter for a 0.6V-1V input/output range and 1.2V output/input

Document Type

Conference Proceeding

Publication Date

1-1-2014

Abstract

© 2014 IEEE. This paper proposes some important contributions in the design of a low voltage and low energy consumption CMOS level up shifter (bqc-ls) as well as to obtain a high performance level down shifter (bqc-ls/rev) based on the structure presented in [1]. The novel level up/down shifters are suitable for multiple clocks and different supply voltages domain logic systems with minimal area and energy consumption. When the pre-layout simulation is realized with UMC 65nm CMOS technology using regular threshold voltage transistors for a high capacitive load (2pF), the active area and the energy-delay product of bqc-ls are lower than that of reported level shifters. However, the layout of bqc-ls and bqc-ls/rev were implemented using low threshold voltage transistors, because the parasitic capacitance by the layout implementation, the maximum capacitive loading condition is 450fF. Even in this case our proposed circuits are very effective for low voltage operation and low energy consumption. The topology of bqc-ls/rev (level down shifter) is equal than that of bqc-ls, and the only difference between them is the size of their output inverter. Thus the active area for bqc-ls/rev is only 2.6% higher than that required for bqc-ls (level up shifter).

Publication Title

Proceedings of the 2014 29th Conference on Design of Circuits and Integrated Systems, DCIS 2014

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