Title

An energy-efficient successive approximation register analog to digital converter in 180nm

Document Type

Conference Proceeding

Publication Date

12-1-2010

Abstract

This paper presents an analog-to-digital converter using state-of-the-art techniques in 180nm process. Making use of charge sharing, asynchronous logic circuitry, scaled digital voltage supply and a novel sampling scheme, this ADC achieves a figure of merit (FOM) of 45fJ per conversion step in simulations. This FOM is close to reference designs reported in 90nm. © 2010 IEEE.

Publication Title

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

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