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Date of Award


Document Type

Campus Access Dissertation

Degree Name

Doctor of Philosophy in Electrical Engineering (PhD)

Administrative Home Department

Department of Electrical and Computer Engineering

Advisor 1

Zhuo Feng

Committee Member 1

Shiyan Hu

Committee Member 2

Chee-Wooi Ten

Committee Member 3

Zhenlin Wang


To evaluate and verify the functional correction and reliability of circuit designs, circuit components (e.g. resistors, capacitors, etc) need to be accurately modeled (e.g. parasitic extraction) and circuit performance requires precise analysis (e.g. simulation and verification). As the technology scaling of nowadays integrated circuits enters nano-scale regime, the traditional flow of circuit designs becomes increasingly challenging due to the rapid growth of circuit complexity brought by more than billions on-chip components. To this end, during the past decades, endless effort has been made to increase the design efficiency via various directions that include but not limited to exploration of advanced algorithms, leveraging the benefits of multi-core/many-core heterogeneous computation platforms.

For full chip parasitic extraction, we propose GPU-friendly data structures and single-instruction-multiple-data (SIMD) parallel algorithm flows to facilitate the FMM-based 3-D capacitance extraction on GPU. Effective GPU performance modeling methods are also proposed to properly balance the workload of each critical kernel in our FMMGpu implementation, by taking advantage of the GPU's concurrent kernel execution technique. Our experimental results show that FMMGpu brings 22X to 30X speedups in capacitance extractions for various test cases.

For circuit simulations, based on recent graph sparsification research, we propose a circuit-oriented general-purpose support-circuit preconditioning (GPSCP) approach to improve the matrix solving time and reduce the memory consumption during SPICE-accurate integrated circuit simulations. Additionally, a performance model-guided graph sparsification approach is proposed to facilitate automatically building a near-optimal preconditioner. Our experimental results for a variety of large-scale integrated circuit designs show that the proposed technique can achieve up to 18X runtime speedups and 7X memory reduction in DC and transient Simulations.

Besides accelerating the analysis by effective preconditioners, we also explore a scalable power grid reduction method for reducing large-scale flip-chip power grids based on recent spectral graph sparsification techniques. In our work, Schur complement and spectral graph sparsification methods are combined to reduce the original large power grid into a much smaller grid while keeping affordable grid density for fast analysis. Extensive experimental results show that our method can scale linearly with power grid sizes and efficiently reduce industrial power grids sizes by 20X without loss of much accuracy in both DC and transient analysis.