Date of Award

2016

Document Type

Open Access Master's Report

Degree Name

Master of Science in Electrical Engineering (MS)

Administrative Home Department

Department of Electrical and Computer Engineering

Advisor 1

Seyed (Reza) Zekavat

Committee Member 1

Saeid Nooshabadi

Committee Member 2

Zhaohui Wang

Abstract

This report presents a new low latency, high resolution and low cost timing synchro- nization technique for digital receivers. Traditional timing synchronization employs Matched filter to perform cross-correlation operation and estimate Time-of-Arrival (TOA) of the signal. Decreasing the latency of the traditional method through over- sampling leads to a higher complexity and it is not viable. Furthermore, to obtain a high-resolution TOA, an extensive bandwidth is required, which results in high system complexity. The proposed method uses single bit quantization to employ XNOR blocks instead of multiplier and accumulator (MAC) blocks in the traditional method. This substantially decreases complexity incorporating less hardware ele- ments in FPGA surface area.

Available for download on Saturday, July 29, 2017

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